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PostPosted: Thu Mar 23, 2017 4:47 am 
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Joined: Fri Dec 23, 2016 5:18 pm
Posts: 41
Location: New Mexico, USA
Tiny030 is yet another Tiny 68K series of pc board in 100mm x 100mm format. Since 68030 is quite similar to the 68020, I chose not to prototype this design. The design has two phases: the first phase is with 8-bit wide boot flash and 8-bit wide static RAM, much like Tiny020. The second phase is a 32-bit wide 32 megabyte dynamic RAM in form of a SIMM 72 module. To pack the design in the 100mm x 100mm, I use a fairly modern CPLD, the Altera's 7128S. All TTL logics are migrated into the CPLD as well as the DRAM controller. I have no experience with DRAM controller so the 10 or so control signals from CPLD to DRAM are not hooked up since it is easier to add wires to pc board than to delete wires.

Received the Tiny030 pc board along with the Tiny302 board. The SIMM72 socket is at the left edge of the pc board. The whole socket is longer than 100mm, but fortunately, the electrical connections just fit within the 100mm constraint. There is room for only one 7-segment display. The 7-seg display is such a useful diagnostic tool that even just one provides significant insight into working of the software/hardware.
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File comment: Tiny030 bare pc board, component side
DSC_24200322.jpg
DSC_24200322.jpg [ 531.53 KiB | Viewed 17 times ]


Phase one components are populated in this picture. The Altera 7128S can be programmed insitu because its I/O pins are pulled up during programming so RAM/Flash/68681 are not asserted during CPLD programming. The CPU double bus faulted and halted during CPLD programming so it is not necessary to manually assert the reset. At 16MHz system clock, RAM and Flash are running with zero wait state. I'll change the oscillator to 25MHz later and RAM/Flash will need to run 1 wait state at that frequency. The 3.6864 crystal in the center of the board didn't oscillate proper--I need to guard band the crystal circuits from other digital signals which I didn't do. Fortunately I have a backup 3.6864 oscillator under the 16MHz clock and it works. Phase one is working now. I'm ready to tackle the DRAM controller and add the 32-meg DRAM module!
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File comment: Tiny030, phase one
DSC_24140322.jpg
DSC_24140322.jpg [ 468.94 KiB | Viewed 17 times ]


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PostPosted: Thu Mar 23, 2017 1:11 pm 
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Joined: Fri Dec 23, 2016 5:18 pm
Posts: 41
Location: New Mexico, USA
This is the schematic of Tiny030


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File comment: Tiny030 schematic
Tiny030_scm.jpg
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