Tiny030 is yet another Tiny 68K series of pc board in 100mm x 100mm format. Since 68030 is quite similar to the 68020, I chose not to prototype this design. The design has two phases: the first phase is with 8-bit wide boot flash and 8-bit wide static RAM, much like Tiny020. The second phase is a 32-bit wide 32 megabyte dynamic RAM in form of a SIMM 72 module. To pack the design in the 100mm x 100mm, I use a fairly modern CPLD, the Altera's 7128S. All TTL logics are migrated into the CPLD as well as the DRAM controller. I have no experience with DRAM controller so the 10 or so control signals from CPLD to DRAM are not hooked up since it is easier to add wires to pc board than to delete wires.

Received the Tiny030 pc board along with the Tiny302 board. The SIMM72 socket is at the left edge of the pc board. The whole socket is longer than 100mm, but fortunately, the electrical connections just fit within the 100mm constraint. There is room for only one 7-segment display. The 7-seg display is such a useful diagnostic tool that even just one provides significant insight into working of the software/hardware.


Phase one components are populated in this picture. The Altera 7128S can be programmed insitu because its I/O pins are pulled up during programming so RAM/Flash/68681 are not asserted during CPLD programming. The CPU double bus faulted and halted during CPLD programming so it is not necessary to manually assert the reset. At 16MHz system clock, RAM and Flash are running with zero wait state. I'll change the oscillator to 25MHz later and RAM/Flash will need to run 1 wait state at that frequency. The 3.6864 crystal in the center of the board didn't oscillate proper--I need to guard band the crystal circuits from other digital signals which I didn't do. Fortunately I have a backup 3.6864 oscillator under the 16MHz clock and it works. Phase one is working now. I'm ready to tackle the DRAM controller and add the 32-meg DRAM module!

This is the schematic of Tiny030

This is the fully populated board. I didn't have 74HCT244 for address mux, so I use 74HCT240 instead. The addresses are inverted, but it doesn't matter since we are talking to RAM. Using 244 or 240 was not a good design choice, however, because it adds more complexity to the timing where delay is needed from first 244 turning off to the second 244 turning on. A multiplexer like 74157 or 74257 would be a better choice. Be that as it may, the DRAM controller is working with a 16 megabyte simm72 DRAM module. At 16MHz system clock, a wait state is needed to access the DRAM which is actually faster than I expected. The refresh is done automatically by the CPLD logic invisible to 68030 using CAS-before-RAS refreshing scheme which steals one bus cycle or 3 clocks. Since a refresh is performed every 250 clocks, this is a 1.2% overhead for using DRAM, an insignificant penalty to performance. The DRAM controllers takes 18 macrocells to implement: 8 for the refresh counter, 5 for CAS-before-RAS refresh logic, and 5 for normal DRAM access. The Altera 7128S has 128 macrocells, so that works. Right now the total macorcells used in the design is 47, or 37%.



Not everything is rosy, there are issues: DRAM access generates significant of power spikes which can cause ground bounces and mess up the CPU operations. I've had intermittent bus errors which is fixed, for now, by adding a couple extra ground wires. I have several surplus DRAM module and one of them have intermittent memory errors at the rate of once every 5-10 minutes. I suspect it is not the DRAM module per se, but a warning sign of excess noises in the system. I added more bypass & filter caps around DRAM, but the problem persisted. A multi layer pcb or grided power/ground 2-layer board is indicated by these problems. There are a couple dozen "blue wires" added to the pc board. 6 of them are for debugging/instrumentation purpose, but still a lot of hand wiring. A board redesign is needed.



I'm pleased with the design, nevertheless. a large memory opens the door for operation system like Linux so maybe I can tell my wife that these boards are "useful" after all!

I am able to run Tiny030 at 24MHz now. However, the poor design choice of using 74244 address buffers instead of the 74157 address multiplexer is now apparent--I need to increase the wait state to 2 waits in order to run at 24MHz. 74157 address multiplexer would've allow 1 wait access.
With DRAM working, now it is possible to eliminate the byte-wide static RAM from the design. In fact, with a bit of trick in CPLD logic, it is even possible to eliminate the boot flash and replace with a small serial flash that copies boot code into DRAM at powering up. This may free up enough board space to think seriously about adding video/IDE/keyboard/mouse interfaces and have a standalone computer in the 100mm x 100mm format. A TinyMac!

Hi Plasmo,
I am continually amazed at what you have accomplished. I want to play with your PCBs. Do you have extras and how much do they cost? Please contact me at computerdoc at sc dot rr dot com. I am seriously interested in these tiny designs!
Kip Koon

Kip,
I'm happy to share my pc boards at my cost which is around $3 plus actual shipping cost. Please PM me for details.

Plasmo,
I also want to play with your PCB. How can I get a PCB?

Kazu,
Design information about the Tinyxxx are posted here:

https://www.retrobrewcomputers.org/doku ... asmo:start

They are incomplete, especially in the software area. This is because the software changes so rapidly, I want to manage them in github, but I still try to figure out how to use github.
You may not want to build Tiny030--it works fine, but there are about 2 dozens wires that need to be hand soldered.
Look over the documentations, let me know what additional information you need. If you are still interested, send me a PM of your address and I'll send your the board of your choice and payment information. If you live in the USA and just want a bare board, it is pretty cheap to mail you a board. The total cost should not exceed $4 per board.

To Plasmo:

Has there been further design changes to this 030 SBC since the April 2017 post? I love to read of your efforts
with the 030 processor and your desire to work also on the 68040 processor. I have both a Mac 040 desktop and
a Mac 040 laptop.

Most of my career I have been a R&D technician doing work on Z-80 and 68K processor systems, but that is in
the past now that I at retirement age, so wish you the best in these efforts with 68xxx designs.

Jes246

Thank you for your interests in my 680x0 efforts. I was hoping to work on Tiny030 this winter (adding a compact flash interface and larger DRAM), but I was distracted with a number of projects revolving around Z280, Z80 and Generic 8-bit processor prototype. Since you have had experiences with Z80, you may find some of these homebrews interesting by Googling TinyZ280, Z280RC, ZZ80RC, Z80SBCRC.

I hope to return to 680x0 and CPU32 soon. I'm in fact designing a 68008 for the Generic 8-bit processor prototype right now. The 68K is the first processor of my career and I had always loved that architecture.
Bill

Hey Plasmo, thanks for Tiny030! I'm working on my own 68030 design and stumbled across it and it actually has been VERY helpful in teaching me. I'm new to more complex CPLD designs and am still in the learning phase. The nCLK was a clever thing I'd not seen before. Thank you! My design will also include running two SIMMs as I'm going to try to go up to 256MB with two 128MB SIMMs.

Regarding the DRAM access, I'm somewhat certain that you can actually make it 0WS (1WS worst case) rather than 2WS at 25Mhz. Note that it requires some assumptions on the part of the DRAMs being used. I've attached a datasheet for a chip on a 72 pin 128MB SIMM I'm using for my design and wanted to run this by you. Please check my work and challenge my assumptions.

At 25Mhz, the 68030 is basically doing 3 clocks per operation, which is 120ns at 25Mhz for a random access memory cycle. trc On this chip is 80ns for the 45ns part, and 110ns on the 60ns part, both of which, in theory, should be doable.

1) Judging by the AccessDRAM_Late.bdf, it looks as if CAS is asserted one cycle later than RAS, which (at 25Mhz) is 40ns. I think this can be shortened to 20ns (trcd is 18ns in this particular part) by doubling the clock input (50Mhz), feeding a /2 to the CPU, and adding additional flops to create necessary delays.

2) tcas Can be shortened as well, down to 20ns (chip requires 12ns minimum).

3) Deassert !CAS one (50mhz) cycle sooner so the !CAS precharge is brought in a bit. It looks like data out is still asserted until !RAS is removed, which you can deassert when !AS goes away. The CPU isn't going to reassert !AS until S1 again, and that's 40ns after !RAS is removed, which meets trp even in worst case -60 parts.

4) You can still do the nCLK trick for switching the external row/column buffers/MUXes.

Thoughts? Very much appreciate. If you have spare boards to buy, I'd love to pick one up. Thank you!

Glad to see someone is interested in 68030 design.

While 68030 takes 3 clock cycles to read, the actual read timing is significantly shorter. Take a close look at the timing diagram, you'll see the nAS is not asserted up to 18nS after falling edge of S0 (timing parameter #9) and data needs to be read 1ns before the falling edge of S4 (timing parameter #27), so you only have 61nS (worst case) for zero wait access at 25MHz. Running at room temperature with nominal 5V, you probably have 70nS and barely able to run with 1 wait with 60nS DRAM.

I do have more blank pc boards if you are interested. If you are in USA, PM me your address, I'll mail you a blank pc board free.
Bill

Thanks Bill! Appreciate the response. I'll take a closer look at things and PM you.

Dang it... I can't PM you because I don't have enough posts, apparently. ;-( Try emailing me at nb at synthcom.com. Would love a board (and to build it)! I have the USBBlaster to program the Altera parts and could build it up pretty quickly. Thank you!