Tiny030 is yet another Tiny 68K series of pc board in 100mm x 100mm format. Since 68030 is quite similar to the 68020, I chose not to prototype this design. The design has two phases: the first phase is with 8-bit wide boot flash and 8-bit wide static RAM, much like Tiny020. The second phase is a 32-bit wide 32 megabyte dynamic RAM in form of a SIMM 72 module. To pack the design in the 100mm x 100mm, I use a fairly modern CPLD, the Altera's 7128S. All TTL logics are migrated into the CPLD as well as the DRAM controller. I have no experience with DRAM controller so the 10 or so control signals from CPLD to DRAM are not hooked up since it is easier to add wires to pc board than to delete wires.

Received the Tiny030 pc board along with the Tiny302 board. The SIMM72 socket is at the left edge of the pc board. The whole socket is longer than 100mm, but fortunately, the electrical connections just fit within the 100mm constraint. There is room for only one 7-segment display. The 7-seg display is such a useful diagnostic tool that even just one provides significant insight into working of the software/hardware.


Phase one components are populated in this picture. The Altera 7128S can be programmed insitu because its I/O pins are pulled up during programming so RAM/Flash/68681 are not asserted during CPLD programming. The CPU double bus faulted and halted during CPLD programming so it is not necessary to manually assert the reset. At 16MHz system clock, RAM and Flash are running with zero wait state. I'll change the oscillator to 25MHz later and RAM/Flash will need to run 1 wait state at that frequency. The 3.6864 crystal in the center of the board didn't oscillate proper--I need to guard band the crystal circuits from other digital signals which I didn't do. Fortunately I have a backup 3.6864 oscillator under the 16MHz clock and it works. Phase one is working now. I'm ready to tackle the DRAM controller and add the 32-meg DRAM module!

This is the schematic of Tiny030

This is the fully populated board. I didn't have 74HCT244 for address mux, so I use 74HCT240 instead. The addresses are inverted, but it doesn't matter since we are talking to RAM. Using 244 or 240 was not a good design choice, however, because it adds more complexity to the timing where delay is needed from first 244 turning off to the second 244 turning on. A multiplexer like 74157 or 74257 would be a better choice. Be that as it may, the DRAM controller is working with a 16 megabyte simm72 DRAM module. At 16MHz system clock, a wait state is needed to access the DRAM which is actually faster than I expected. The refresh is done automatically by the CPLD logic invisible to 68030 using CAS-before-RAS refreshing scheme which steals one bus cycle or 3 clocks. Since a refresh is performed every 250 clocks, this is a 1.2% overhead for using DRAM, an insignificant penalty to performance. The DRAM controllers takes 18 macrocells to implement: 8 for the refresh counter, 5 for CAS-before-RAS refresh logic, and 5 for normal DRAM access. The Altera 7128S has 128 macrocells, so that works. Right now the total macorcells used in the design is 47, or 37%.



Not everything is rosy, there are issues: DRAM access generates significant of power spikes which can cause ground bounces and mess up the CPU operations. I've had intermittent bus errors which is fixed, for now, by adding a couple extra ground wires. I have several surplus DRAM module and one of them have intermittent memory errors at the rate of once every 5-10 minutes. I suspect it is not the DRAM module per se, but a warning sign of excess noises in the system. I added more bypass & filter caps around DRAM, but the problem persisted. A multi layer pcb or grided power/ground 2-layer board is indicated by these problems. There are a couple dozen "blue wires" added to the pc board. 6 of them are for debugging/instrumentation purpose, but still a lot of hand wiring. A board redesign is needed.



I'm pleased with the design, nevertheless. a large memory opens the door for operation system like Linux so maybe I can tell my wife that these boards are "useful" after all!

I am able to run Tiny030 at 24MHz now. However, the poor design choice of using 74244 address buffers instead of the 74157 address multiplexer is now apparent--I need to increase the wait state to 2 waits in order to run at 24MHz. 74157 address multiplexer would've allow 1 wait access.
With DRAM working, now it is possible to eliminate the byte-wide static RAM from the design. In fact, with a bit of trick in CPLD logic, it is even possible to eliminate the boot flash and replace with a small serial flash that copies boot code into DRAM at powering up. This may free up enough board space to think seriously about adding video/IDE/keyboard/mouse interfaces and have a standalone computer in the 100mm x 100mm format. A TinyMac!

Hi Plasmo,
I am continually amazed at what you have accomplished. I want to play with your PCBs. Do you have extras and how much do they cost? Please contact me at computerdoc at sc dot rr dot com. I am seriously interested in these tiny designs!
Kip Koon

Kip,
I'm happy to share my pc boards at my cost which is around $3 plus actual shipping cost. Please PM me for details.

Plasmo,
I also want to play with your PCB. How can I get a PCB?

Kazu,
Design information about the Tinyxxx are posted here:

https://www.retrobrewcomputers.org/doku ... asmo:start

They are incomplete, especially in the software area. This is because the software changes so rapidly, I want to manage them in github, but I still try to figure out how to use github.
You may not want to build Tiny030--it works fine, but there are about 2 dozens wires that need to be hand soldered.
Look over the documentations, let me know what additional information you need. If you are still interested, send me a PM of your address and I'll send your the board of your choice and payment information. If you live in the USA and just want a bare board, it is pretty cheap to mail you a board. The total cost should not exceed $4 per board.