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PostPosted: Thu Feb 18, 2016 9:19 pm 
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Joined: Thu Feb 18, 2016 9:08 pm
Posts: 1
The M68000UM says that the Scc instructions on a register destination consume 6 or 4 instructions, depending on if the condition was true or false, while a memory destination always consume 8 cycles.

The SCC implementation in CODE8.CPP seemingly implements this;

Code:
  if (inst & 0x0030 == 0)
    inc_cyc (check_condition (condition) ? 6 : 4);
  else
    inc_cyc (8);

but the simulator always reports 8 cycles. This is due to a subtle bug: the fact that == is evaluated before &, making the expression always evaluate to false (and 8 cycles) - the expression need an extra pair of parens:

Code:
  if ( (inst & 0x0030) == 0)
    inc_cyc (check_condition (condition) ? 6 : 4);
  else
    inc_cyc (8);


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PostPosted: Fri Feb 19, 2016 12:22 pm 
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Joined: Thu Dec 16, 2004 6:42 pm
Posts: 1048
I love bug reports that provide the solution :happy2

Thanks for the extra effort.

_________________
Prof. Kelly


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