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PostPosted: Fri Aug 21, 2009 1:47 pm 
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Joined: Wed Jul 29, 2009 5:36 pm
Posts: 9
Location: Ptolemaios
Why are the rows for opcodes BFCHG up to BFTST are highlighted with gray?
I am also interested in using those opcodes especially BFEXTS, BFEXTU, and BFINS but I don't know how to count the offset for data registers and I always get an illegal instruction error upon running it. Please teach me how and what values to put for the 'o' part of the syntax. An example would be of great help.

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PostPosted: Fri Aug 21, 2009 3:34 pm 
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Joined: Thu Dec 16, 2004 6:42 pm
Posts: 1087
Good question.

The bit field instructions are highlighted with gray because they are not 68000 instructions. Bit field instructions were not introduced until the 68020. The EASy68K implementation of bit field instructions are limited to 68000 addressing modes.

Here is a rough example that I used for testing. I can provide more details if this doesn't answer your question.

Code:
        opt     bit
START   org     $1000
        move.l  #$AAAAAAAA,D0
        move.l  #1,D1
        move.l  #2,D2
        move.l   #$2000,D3
        lea     data1,A1

        bfchg   D0{D1:D2}
        bfchg  (A1){8:D2}
        bfchg  (1,A1){8:D2}
        bfchg  (1,A1,D1){8:D2}
        bfchg  $2000{8:D2}
        bfchg  $2000.L{8:D2}
*        bfchg  $1000(PC){8:D2}      ; invalid addressing mode
*        bfchg  $1000(PC,D4){8:D2}   ; invalid addressing mode

        bfclr   D0{D1:D2}
        bfclr  (A1){8:D2}
        bfclr  (1,A1){8:D2}
        bfclr  (1,A1,D1){8:D2}
        bfclr  $2003{8:D2}
        bfclr  $2004.L{8:D2}
*        bfclr  $1000(PC){8:D2}      ; invalid addressing mode
*        bfclr  $1000(PC,D4){8:D2}   ; invalid addressing mode

        bfexts  D0{0:D2},D4
        bfexts  (A1){1:D2},D4
        bfexts  (1,A1){2:D2},D4
        bfexts  (1,A1,D1){3:D2},D4
        bfexts  $2000{4:D2},D4
        bfexts  $2000.L{5:D2},D4
        bfexts  $2000(PC){6:D2},D4
        bfexts  *+2(PC,D3){7:D2},D4

        bfextu  D0{0:D2},D4
        bfextu  (A1){1:D2},D4
        bfextu  (1,A1){2:D2},D4
        bfextu  (1,A1,D1){3:D2},D4
        bfextu  $2000{4:D2},D4
        bfextu  $2000.L{5:D2},D4
        bfextu  $2000(PC){6:D2},D4
        bfextu  *+2(PC,D3){7:D2},D4

        bfffo  D0{0:D2},D4
        bfffo  (A1){1:D2},D4
        bfffo  (1,A1){2:D2},D4
        bfffo  (1,A1,D1){3:D2},D4
        bfffo  $2000{4:D2},D4
        bfffo  $2000.L{5:D2},D4
        bfffo  $2000(PC){6:D2},D4
        bfffo  *+2(PC,D4){7:D2},D4

      move.l   #-1,D4
        bfins  D4,D0{0:D2}
        bfins  D4,(A1){1:D2}
        bfins  D4,(1,A1){2:D2}
        bfins  D4,(1,A1,D1){3:D2}
        bfins  D4,$2000{4:D2}
        bfins  D4,$2000.L{5:D2}
*        bfins  D4,$1000(PC){6:D2}   ; invalid addressing mode
*        bfins  D4,*-2(PC,D4){7:D2}   ; invalid addressing mode

        bfset   D0{D1:D2}
        bfset  (A1){1:D2}
        bfset  (1,A1){2:D2}
        bfset  (1,A1,D1){3:D2}
        bfset  $2000{4:D2}
        bfset  $2000.L{5:D2}
*        bfset  $1000(PC){6:D2}      ; invalid addressing mode
*        bfset  *+5(PC,D4){7:D2}   ; invalid addressing mode

        bftst   data4{10:5}
        bftst   D0{D1:D2}
        bftst  (A1){0:D2}
        bftst  (1,A1){1:D2}
        bftst  (1,A1,D1){2:D2}
        bftst  $2000{3:D2}
        bftst  $2000.L{4:D2}
        bftst  $2000(PC){5:D2}
        bftst  *+2(PC,D4){6:D2}
       
       
        stop    #$2000
       
        org     $2000
data1   dc.l    $AAAAAAAA
data2   dc.l    $55555555
        dc.l    $55555555
data3   dc.l    $AAAAAAAA
        dc.l    $AAAAAAAA
data4   dc.l    $00800000
        end     START

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PostPosted: Fri Aug 21, 2009 4:12 pm 
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Joined: Wed Jul 29, 2009 5:36 pm
Posts: 9
Location: Ptolemaios
profkelly wrote:
Code:
        bfextu  D0{0:D2},D4
        bfextu  (A1){1:D2},D4
        bfextu  (1,A1){2:D2},D4
        bfextu  (1,A1,D1){3:D2},D4
        bfextu  $2000{4:D2},D4
        bfextu  $2000.L{5:D2},D4
        bfextu  $2000(PC){6:D2},D4
        bfextu  *+2(PC,D3){7:D2},D4

        bfffo  D0{0:D2},D4
        bfffo  (A1){1:D2},D4
        bfffo  (1,A1){2:D2},D4
        bfffo  (1,A1,D1){3:D2},D4
        bfffo  $2000{4:D2},D4
        bfffo  $2000.L{5:D2},D4
        bfffo  $2000(PC){6:D2},D4
        bfffo  *+2(PC,D4){7:D2},D4

Now, I get it. I may still use these opcodes..
Are BFEXTU and BFFFO part of the 6800 opcode? Even before 68020?
More questions, eto.., should I always use a data register for the 'w' (width) part?
[EDIT] I tried using immediate values, it works. I wonder why I got illegal instruction error earlier.[/EDIT]
What do call that addressing with *+2, is it a variation for the relative mode, ne?
Thank you very much, profkelly.

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PostPosted: Fri Aug 21, 2009 10:21 pm 
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Joined: Thu Dec 16, 2004 6:42 pm
Posts: 1087
BFEXTU and BFFFO are not 68000 opcodes. They were first introduced in the 68020.

*+2 is not a separate addressing mode. It is evaluated by the assembler as the current address plus 2. The asterisk * may be used to represent the current address in instructions.

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