I am near the end of a project to verify a 68000 FPGA design which
involved running millions of random but legal instructions through
the easy68k simulator and our RTL version of the 68000 to see where
Those of you who read the easy68k forum will see that I have made
quite a number of posts recently. Many of them have been about
"corner cases" in the 68000 design that a real compiler would never
hit. Even so, most of them were quickly fixed in new releases and I
could continue verifying.
I want to thank all the people contributing to easy68k, especially
profkelly and clive. Here at Millogic, we have paid for support that
wasn't as good or as fast.