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PostPosted: Sun Mar 20, 2011 12:01 am 
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Joined: Sat Mar 19, 2011 4:32 pm
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Location: Germany
Hi all, I'm just a hobbyist who wants to make his own 68K computer around a 68010. I'm looking for this book - or rather, any book that tells me how to build a system around this chip and not just give me details about the instruction set/its peripheral chips. I'd be willing to pay (just not the crazy prices Amazon charges) for shipping and the book through Paypal. I live in Germany.

EDIT: BTW thanks for posting DTACK Grounded on this site. It's quite entertaining.


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PostPosted: Mon Mar 21, 2011 5:17 pm 
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Joined: Thu Dec 16, 2004 6:42 pm
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ritchan wrote:
EDIT: BTW thanks for posting DTACK Grounded on this site. It's quite entertaining.


DTACK Grounded archives are courtesy of my late friend Paul R. Santa-Maria. I have a few issues that still need to be scanned and posted to complete Paul's project. (Student Project :D) I also have a number of 68000 books that were part of Paul's library. They are at a different location so I'm not sure if the book you are looking for is part of the collection. I'll check this weekend.

_________________
Prof. Kelly


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PostPosted: Mon Mar 21, 2011 6:26 pm 
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Joined: Mon Jul 26, 2010 11:43 pm
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Location: Aurora, IL
Amazon has relatively cheap shipping in the US ($4), but international shipping of books is expensive, and Amazon's fees to sellers are not insignificant. You need to find the book with an affiliate who is close to you.

You could also try Alibris.com which is easier to find coupons for, then again finding people doing book arbitrage in Europe/Germany would be the way to go, it can't be a purely US business.

Most of the Motorola/PHI manuals from the era are now available as PDF's, the original 68000 manual went into quite laboured detail of the bus timings. Today's higher speed components should make life a lot easier. Do you want to build it with 74 series logic, PALs, FPGA's, etc?

Alan Clement's books have some worked circuits as I recall.

The web has several resources too
http://www.kmitl.ac.th/~kswichit/68k/68k.html
http://www.chd.dyndns.org/sbc/


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PostPosted: Mon Mar 21, 2011 7:00 pm 
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Joined: Sat Mar 19, 2011 4:32 pm
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Location: Germany
Thanks for the replies. I ended up getting a friend to use his Amazon account to buy me a used 3rd edition from the UK for about 30EURs+3 shipping. He owed me anyway after I got him a cheap GTS250 with EVGA Bucks :D

I've been reading a 68K book by Wilcox at the local library, and it talks about wiring up a 555 timer and resistors and various caps to get a RESET signal. The first link really helped in that regard, because it showed that all that complex crap can be replaced by a MCP120. Although I still have to get these 7407s, whatever they are. Technology progress is great!

The RTC circuit can also be replaced with a DS12887. For this particular one with the 68010L10, I am hoping to go with as passive components as possible, using lots of ICs available today to replace lots of small components. If something can be consolidated into a black DIP package, I'll take it.

For the follow up project, though, which involves a 68040 or 68060 and maybe another 68040/68060 in SMP fashion and an expandable bus and a VGA capable chip, and a sound synthesizer, and of course 1 or 2 serial ports, I will probably be looking at higher end things like making a PCB and soldering a socket into it, as well as a PLD or FPGA for all the glue logic, like address decoding.

I have my doubts as to whether a FPGA can simulate address decoding fast enough, though. Any ideas?


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PostPosted: Mon Mar 21, 2011 7:54 pm 
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Location: Aurora, IL
I haven't looked at the 68040+ parts, but I think such a design would be quite complicated to pull off. Buy an old Mac board and hack it.

I've got some boards with 68E020 and 68881/68882 parts, and the logic there would easily work with a CPLD or FPGA. One of the designs has two 68EC020 parts in an dual configuration (Master/Slave) each with their own local RAM, with the slave's RAM mapped into a Master's address space. The Master downloads and starts the code in the slave.

Pretty much any power-on-reset circuit using the MCP120 is going to be incredibly more reliable than one cobbled together with R-C networks and timers.


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PostPosted: Mon Mar 21, 2011 11:29 pm 
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Location: Germany
Other than the widened address and data buses, what would make it more complicated? It's not like I'll have to implement some cache coherency algorithm... all I wanna do is have it run NetBSD :D Seriously speaking though the idea of the second project is to see how useful of a system I can build once I remove all the limitations associated with old systems - little RAM, slow disks, slow buses especially... and I see in the end if I end up with a system that's tolerably fast to run irssi or something. midori (web browser) might be CPU bound from the very beginning though.

I was thinking of each CPU having its own 8MB "local store" of SRAM, then going through a FPGA a buttload of DRAM, like say 64MB-128MB. Each CPU can access the other's SRAM, and both can access the DRAM, but probably not at the same time unless they both need the same data.


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PostPosted: Tue Mar 22, 2011 3:07 pm 
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Location: Aurora, IL
Like I said, I haven't looked at the 68040 in any detail, however given it's 4x performance, I'd suppose the bus timings are a lot more aggressive.

But you're right, probably no point in building a cache if you can populate the board with single cycle SRAM. That said I don't think 64MB is much RAM these days, I can get that in a single 133 MHz SDRAM ram part in a 9x9mm foot print, and build a 400 MHz ARM9 design with that and 1GB of NAND in the shadow of the 68040 PGA.

Have you looked at the ColdFire / NetBurner devices?


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PostPosted: Thu Jan 01, 2015 7:04 pm 
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have you completed your project ?


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