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PostPosted: Thu May 03, 2012 1:11 pm 
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Joined: Mon Mar 19, 2012 9:11 pm
Posts: 17
roxl.w
====
With an an initial value of X=0, I think the easy68k simulator gets the wrong
result for roxl.w in the following code snippet.

move.l #$009b35f5,d4
move.l #$5f507d00,d5
roxl.w d4,d5

M68000prm.pdf says that the modulo 64 value of D4 will be used as the
rotate count. An roxl.w is a modulo 17 rotate which means that d4
contains the equivalent of a rotate by 2.

The easy68k simulator gets the right value in d5 (5f50f400) but X=0. I
think it should be X=1.

lsr.w
===
I think the easy68k simulator gets the wrong result for lsr.w in the
following code snippet.

move.l #$08090aa7,d2
move.l #$000000E8,d6
lsr.w d6,d2

M68000prm.pdf says that the modulo 64 value of D6 will be used as the
shift count. This would be a 40 bit shift which should clear X and C and
the low 16 bits of D2 . The simulator gets D2 right but X=1 and C=1.

thanks,
aboxer


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PostPosted: Thu May 03, 2012 5:57 pm 
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Joined: Mon Jul 26, 2010 11:43 pm
Posts: 198
Location: Aurora, IL
Real HW

Code:
Initial conditions

C = 0
V = 0
Z = 0
N = 0
X = 0

Final conditions

D4=009B35F5
D5=5F50F400

C = 1
V = 0
Z = 0
N = 1
X = 1


Code:
Initial conditions

C = 1
V = 1
Z = 1
N = 1
X = 1

Final conditions

D4=009B35F5
D5=5F50F402

C = 1
V = 0
Z = 0
N = 1
X = 1


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PostPosted: Thu May 03, 2012 6:04 pm 
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Joined: Thu Dec 16, 2004 6:42 pm
Posts: 1039
Confirmed on real 68000, X should be 1.

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Prof. Kelly


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PostPosted: Thu May 03, 2012 6:09 pm 
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Joined: Mon Jul 26, 2010 11:43 pm
Posts: 198
Location: Aurora, IL
You edited while I tried ROXL, For LSR

Code:
D2 = 08090000
D6 = 000000E8

C = 0
V = 0
Z = 1
N = 0
X = 0


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PostPosted: Mon May 14, 2012 1:41 pm 
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Posts: 1039
Corrected (I think?) in Sim68K v5.12.4.
I did not write the original code which makes it more problematic to debug. I am not 100% sure my changes are correct.

Correction
UTILS.CPP: cc_update function,
Code:
switch (c) {
    case CASE_2 :    // ROR, ROXR   CK 5-2012
        r %= (m+2);
        c_bit = ((dest >> (r-1)) & 1) ? true : false;
        break;
    case CASE_3 :    // LSL, ROL, ROXL   CK 5-2012
        r %= (m+2);
        c_bit = ((dest >> (m-r+1)) & 1) ? true : false;
        break;
    case CASE_7 :    // ASR      CK 1-25-2008
        if (r > m)
            r = m+1;
        c_bit = ((dest >> (r-1)) & 1) ? true : false;
        break;
   case CASE_8 :    // LSR CK 5-2012
        if (r > m+1)        // if shift count > size
            c_bit = false;
        else {
            r %= (m+2);
            c_bit = ((dest >> (r-1)) & 1) ? true : false;
        }
        break;
};


CODE7.CPP, SHIFT_ROT function,
Code:
    } else {      // else shift right
        if (shift_count >= 32)    // 68000 does modulo 64 shift, c++ does modulo 32
            shift_result = 0;
        else
            shift_result = (unsigned)(EV1 & size) >> shift_count;
        put (EA1, shift_result, size);
        value_of (EA1, &EV1, size);
        cc_update (GEN, GEN, GEN, ZER, CASE_8,        // ck 5-2102
                  source, dest, EV1, size, shift_count);
    }
        break;

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Prof. Kelly


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PostPosted: Tue May 15, 2012 6:30 pm 
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Joined: Mon Mar 19, 2012 9:11 pm
Posts: 17
The following snip of code sets X=0 and C=0 on simulator (v5.12.3)

move.l #0, d1
move.l #$ffffffff,d4
move #$10,ccr
roxl.b d4,d1

d4 is a modulo 64 rotate count of 63 decimal. An roxl.b is equivalent
to a 9 bit rotator including X and a byte of d1. Since we start the rotate
with X=1 we should end it with x=1 and C=1.

thanks,
aaron boxer


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