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PostPosted: Tue May 22, 2012 4:02 pm 
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Joined: Mon Mar 19, 2012 9:11 pm
Posts: 17
M68000_Users_Manual.pdf indicates that the PC of the instruction after
the illegal one will be stored on the stack. The simulator stores the PC of
the illegal instruction.

I know that there is a similar thread from 2005 indicating that Bus Error
and Address traps do the same thing (link below) and it won't be fixed.
I just wanted to document the behavior to save others some debugging
time. It didn't take me too long :)

http://www.easy68k.com/EASy68Kforum/vie ... hlight=bus

aaron boxer
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PostPosted: Fri Jun 01, 2012 1:09 pm 
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This one now seems a little more important than I first thought. Since the
68000 has no breakpoint instruction, debuggers may use illegal instruction
traps as a mechanism for implementing breakpoints.

In this case, knowing what PC the 68000 silicon pushes on the stack is
important for proper breakpoint behavior. Does anyone know what the
silicon does?

thanks,
Aaron Boxer
Millogic


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PostPosted: Sat Jun 02, 2012 12:12 pm 
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All the 68000 debuggers I'm aware of use a TRAP instruction for breakpoint setting.

Once the breakpoint is hit the original word is replaced and the instruction can be traced before the breakpoint is set again.

You couldn't safely use an illegal instruction because it may not have been illegal across the whole family or on future parts. Not so much of a problem now of course.


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PostPosted: Thu Jun 14, 2012 6:39 pm 
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Isn't ILLEGAL architecturally defined?

0100101011111100 ILLEGAL
$4AFC


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PostPosted: Thu Jun 14, 2012 8:08 pm 
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According to the MC68000 user manual the current program counter is pushed on the stack.

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PostPosted: Fri Dec 14, 2012 10:51 pm 
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Confirmed on real hardware.

The Motorola Educational Computer Board.

2000: NOP
2002: NOP
2004: ILLEGAL
2006: NOP

2004 is pushed on the stack when the ILLEGAL instruction executes.

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PostPosted: Fri Jan 10, 2014 6:16 am 
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Once the breakpoint is hit the original word is replaced and the instruction can be traced before the breakpoint is set again.

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PostPosted: Fri Jan 10, 2014 3:59 pm 
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That's certainly a common approach for code that's in RAM. For a ROM an ICE would do address matching and feed ILLEGAL (or whatever) into the initial fetch cycle to implement a "hardware" breakpoint. Modern CPU tend to have debug units built in to do the address matching and faulting, but those still tend to be limited resource and either patching in breakpointing instructions, or adding them to the compilers code generation stream are still quite popular for people who want hundreds of breakpoints. The other would be to call a trapping subroutine with a parameter.


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